The present invention relates to a memory testing apparatus and a memory testing method, and more specifically to the structure of a fail information memory in a memory testing apparatus and a memory testing method using a fail information memory.
In the prior art, a redundant design is adopted in a semiconductor memory in order to remedy the whole of a memory device from becoming defective because of one bit memory cell defect or one row or column defect.
Referring to FIG. 1, there is shown a block diagram of an example of a conventional memory of the redundant design. The shown memory is so configured that when a defective row or column within a memory cell array 200 of the semiconductor memory is accessed, a redundant row 203 or a redundant column 204 is selected in place of the defective row or column by a redundant X decoder 205 or a redundant Y decoder 206, with the result that since the memory cell array 200 containing the defective row or column is remedied, the yield of production is elevated.
Explaining the semiconductor memory shown in FIG. 1, in the memory cell array 200 there is accessed a memory cell designated by a word line selected by an X decoder 201, which receives and decodes an X address and selects a word line designated by the X address, and a digit line selected by a Y decoder 202, which receives and decodes a Y address and selects a digit line designated by the Y address, by turning on a not-shown Y switch connected in series in the digit line designated by the Y address. In this access, if the memory cell designated within the memory cell array 200 is defective, the access to the designated memory cell is replaced by an access to a redundant cell included in the redundant row 203 or the redundant column 204, by action of the redundant X decoder 205 or the redundant Y decoder 206. Here, in order to distinguish the memory cells included in the memory cell array 200 from the redundant cells, each memory cell included in the memory cell array 200 will be called a xe2x80x9cmain cellxe2x80x9d, and the memory cell array 200 will be called a xe2x80x9cmemory cell arrayxe2x80x9d in this specification.
When a defective cell is detected at a wafer test in a semiconductor memory fabricating process, the redundant row or the redundant column is set by cutting off a fuse in a circuit provided in the semiconductor memory of the redundant design. Here, replacement of the defective cell by the redundant cell in the semiconductor memory of the redundant design is ordinarily executed by various methods, for example, the cutting-off of the fuse, a laser annealing diffusion, an EEPROM, a metal fuse, etc. However, since this does not have a direct relation to the subject of the present invention, further explanation will be omitted.
A memory tester used for detecting a defective in the semiconductor memory at the wafer test or at a final test after the semiconductor memory is assembled, includes a fail information memory for storing fail information.
In the wafer test, the fail information stored in the fail information memory of the memory tester is read out from the fail information memory, and is stored as a fail bit map information in a host computer of the memory tester. After the wafer test, in the semiconductor memory of the redundant design, the redundant row or the redundant column is set on the basis of the fail bit map by the fuse cutting-off or another means.
Referring to FIG. 2, there is shown a functional block diagram illustrating the construction of one example of a conventional memory tester. As shown in FIG. 2, the conventional memory tester includes a timing generator (TG) 100 for generating various timings including a timing of a test cycle, an edge timing of an applied waveform, a strobe timing of a comparator, and others, an algorithmic pattern generator (ALPG) 102 for generating various address patterns and data including a march, a galloping, and others, a programmable data selector (PDS) 103 for allocating a pattern supplied from the algorithmic pattern generator (ALPG) 102 to arbitrary pins on the basis of a test program, a formatter (FC) 104 for variably controlling the format of a waveform to be applied, a driver circuit 105 for applying an input pattern to input terminals of a device under test (DUT) 108, a comparator circuit 106 for receiving and comparing output signals from the device under test (DUT) 108, a digital comparator (DC) 107 for comparing the comparison result outputted from the comparator circuit 106 with a desired value pattern, and a fail information memory 101 receiving the comparison result outputted from the digital comparator (DC) 107 for storing the fail information for each test cycle and in accordance with a test address.
Referring to FIG. 3, there is shown a block diagram showing the construction of one channel of a comparison function in the conventional memory tester shown in FIG. 2, although the comparison function actually includes a plurality of channels. In FIG. 8, a voltage outputting circuit (VO) 109 generates a reference voltage to be compared with the output signal of the device under test (DUT), specifically, a high level reference voltage and a low level reference voltage. The comparator 106 compares the output signal of the device under test (DUT), with the reference voltages supplied from the voltage outputting circuit (VO) 109, and outputs the result of the comparison to the digital comparator (DC) 107. The digital comparator (DC) 107 is controlled by the strobe signal supplied from the timing generator (TG) 100 to compare the comparison result outputted from the comparator 106 with an expect value data generated in the algorithmic pattern generator (ALPG) 102 and pin-allocated by the programmable data selector (PDS) 103.
As shown in FIG. 3, the fail information memory 101 is provided for each comparator channel, and when the result of the comparison executed in the digital comparator (DC) 107 shows a xe2x80x9cfailxe2x80x9d, the fail information is written into the fail information memory 101 in accordance with the address outputted from the algorithmic pattern generator (ALPG) 102, namely, the reading address for the device under test when the xe2x80x9cfailxe2x80x9d occurs.
However, a specific proposal and development have not yet been made in connection with the architecture of a memory tester having a fail information memory corresponding to the redundant cells in the semiconductor memory of the redundant design.
Here, consideration will be made on the case that the semiconductor memory of the redundant design is tested by use of the conventional memory tester mentioned above. In this case, the redundant cells in the semiconductor memory of the redundant design are tested (for example, after data is written to the redundant cells, data is read out from the redundant cells). If fail information of the redundant cells is written to a fail information memory, it is inevitably necessary to increase the memory capacity of the fail information memory. This is disadvantageous.
Now, this problem will be described in detail on the assumption that the fail information of the redundant cells in the device under test is written to a fail information memory of the existing memory tester.
Here, in the wafer test, an address space of the semiconductor memory of the redundant design, which is accessed by the memory tester by setting the semiconductor memory of the redundant design to a test mode, is composed of a combination of an address space of the main cell array and an address space of the redundant cell array. On the other hand, after shipment of a semiconductor memory product, since replacement of defective cells in the main cell array by redundant cells has been finished within the inside of the semiconductor memory, the address space of the semiconductor memory accessible to a user corresponds to the main cell array.
When the semiconductor memory of the redundant design shown in FIG. 1 is tested by use of the conventional memory tester shown in FIGS. 2 and 3, it may be considered that the fail information memory 101 has an arrangement as shown in for example FIG. 4. The fail information memory shown in FIG. 4 corresponds to the fail information memory 101 shown in FIG. 3, but is so configured to receive the comparison results (channel data bits D0 to D3) outputted from respective digital comparators of a plurality of comparator channels. Here, it is to be noted that FIG. 4 shows an imaginary arrangement that the inventor derived from the prior art shown in FIGS. 1 to 3. Therefore, the example shown in FIG. 4 will be called an xe2x80x9cimaginary prior art examplexe2x80x9d in this specification.
Referring to FIG. 4, the fail information memory 101 includes a plurality of fail information memories 1010 to 1013 corresponding to respective channels xe2x80x9c0xe2x80x9d to xe2x80x9c3xe2x80x9d of a plurality of comparator channels (four channels in the example shown in FIG. 4).
In the imaginary prior art example shown in FIG. 4, the channel data bit DO is the comparison result outputted from the digital comparator (107 in FIG. 2) for the comparator channel xe2x80x9c0xe2x80x9d, and the channel data bits D1, D2 and D3 are the comparison result outputted from the digital comparators for the comparator channels xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d, respectively. These channel data bits D0 to D3 are outputted in parallel to one another from the respective digital comparators for the comparator channels xe2x80x9c0xe2x80x9d to xe2x80x9c3xe2x80x9d at the same timing defined by the strobe signal (programmed at a predetermined timing in a test cycle).
The channel data bit D0 is brought to a low level when the comparison result outputted from the digital comparator shows a xe2x80x9cfailxe2x80x9d, and to a high level when the comparison result outputted from the digital comparator shows a xe2x80x9cpassxe2x80x9d. This channel data bit D0 is inputted to a chip select terminal CSB (where the tail end character xe2x80x9cBxe2x80x9d indicates a low active signal) of the fail information memory 1010. When the channel data bit D0 indicates the xe2x80x9cfailxe2x80x9d (the low level), the chip select terminal CSB of the fail information memory 1010 is activated, and therefore, a high level signal supplied to a data input terminal D IN of the fail information memory 1010 is written to a cell within the fail information memory 1010 selected by the address when the xe2x80x9cfailxe2x80x9d occurs (namely, the addresses A0 to A22 supplied from the algorithmic pattern generator (ALPG) 102). Here, in the imaginary prior art example shown in FIG. 4, a write enable terminal WEB (where the tail end character xe2x80x9cBxe2x80x9d indicates a low active signal) of the fail information memory 1010 is fixed to a low level, so that the fail information memory 1010 is maintained in a write enable condition.
On the other hand, when the channel data bit D0 indicates the xe2x80x9cpassxe2x80x9d (the high level), the chip select terminal CSB of the fail information memory 1010 is inactivated so that none is written into the fail information memory 1010.
The above explanation will be applied similarly to the fail information memories 1011 to 1013 for the other channel data bit D1 to D3.
Here, the arrangement of the above mentioned fail information memory is considered. In order to test, as a simple example, the semiconductor memory of the redundant design which comprises the main cell array (200 in FIG. 1) having 1024 rows (1K) and 1024 columns (1K) and therefore having a memory capacity of 1 Mbits and four redundant rows (203 in FIG. 1) added to the main cell array, it is necessary to add a memory capacity of 4xc3x971K cells for the redundant rows to the fail information memory having the memory capacity of 1 Mbits for the main cell array. In FIG. 4, the hatched portion X RED indicates a fail information memory portion for the redundant rows.
In other words, as an address space of the fail information memory, the X address is changed from 10 bits of the fail information memory for the main cell array to 11 bits. This means that, as shown in FIG. 4, it is necessary to add, as a fail information memory for the redundant rows, a fail information memory having the same memory capacity as that of the fail information memory for the main cell array, to the fail information memory for the main cell array. As a result, two times the memory capacity of the conventional fail information memory is required for the fail information memory for the main cell array of the semiconductor memory of the device under test (a conventional fail information memory) and the fail information memory for the redundant rows.
Furthermore, if not only the redundant rows but also the redundant columns are tested and the fail information of all the redundant cells are stored in the fail information memory, it is necessary to prepare a fail information memory having four times the memory capacity required for the test of the main cell array.
Accordingly, for each of the channel data bits D0 to D3, it is necessary to prepare the fail information memory having four times the memory capacity of the conventional fail information memory. As a result, the memory capacity of the fail information memory provided in the memory tester becomes large.
Accordingly, it is an object of the present invention to provide a memory testing apparatus and a memory testing method which have overcome the above mentioned problems.
Another object of the present invention is to provide a memory testing apparatus and a memory testing method, capable of reducing the memory capacitor of the fail information memory required for testing the redundant cells in the semiconductor memory of the redundant design.
Still another object of the present invention is to provide a memory testing apparatus and a memory testing method, capable of reducing the memory capacitor of the fail information memory required for testing the redundant cells in the semiconductor memory of the redundant design, and also capable of speeding up a writing of fail information of the redundant cells into the fail information memory.
The above and other objects of the present invention are achieved in accordance with the present invention by a memory testing apparatus for testing a semiconductor memory, comprising:
means receiving respective comparison results outputted from a plurality of comparators, each of which compares an output signal outputted from a semiconductor memory under test with an expected value, and an address supplied to the semiconductor memory under test, and for synthesizing an address for a fail information memory; and
means for writing fail information into the fail information memory at the address synthesized, when at least one of the comparison results outputted from the plurality of comparators indicates a xe2x80x9cfailxe2x80x9d,
whereby a corresponding number of fail information outputted from the plurality of comparators is written into one cell within the fail information memory.
Specifically, the memory testing apparatus comprises:
a plurality of main cell fail information memories for a main cell array in a semiconductor memory under test, the plurality of fail information memories being provided for a corresponding number of comparator channels, respectively; and
one redundant cell fail information memory provided for redundant cells in the semiconductor memory under test, one for the plurality of main cell fail information memories, so that a test result of the redundant cells in the semiconductor memory under test is written into the redundant cell fail information memory.
According to another aspect of the present invention, there is provided a memory testing method for testing a semiconductor memory having redundant cells in addition to a main cell array, as a device under test, by use of a memory testing apparatus,
the memory testing apparatus comprising:
a plurality of main cell fail information memories for the main cell array in the semiconductor memory under test, the plurality of fail information memories being provided for a corresponding number of comparator channels, respectively; and
one redundant cell fail information memory provided for the redundant cells in the semiconductor memory under test, one for the plurality of main cell fail information memories, so that a test result of the redundant cells in the semiconductor memory,
wherein, when at least one of respective comparison results outputted from a plurality of comparators, each of which compares an output signal outputted from the semiconductor memory under test with an expected value, indicates a xe2x80x9cfailxe2x80x9d, an address is synthesized from the respective comparison results outputted in parallel from the plurality of comparator and an address supplied to the semiconductor memory under test when the xe2x80x9cfailxe2x80x9d occurs, and fail information is written into the redundant cell fail information memory at the address thus synthesized, so that fail information represented by a plurality of fail information bits outputted in parallel from the plurality of comparators is written into one cell within the fail information memory with one writing access.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.